This invention relates to a method for reducing thermal stress in a semiconductor wafer caused during rapid thermal processing.
A major problem faced by the field of rapid thermal processing or (xe2x80x9cRTPxe2x80x9d) has been the uniformity of heating semiconductor wafers, such as silicon wafers, treated in rapid thermal processors. A semiconductor wafer/device to be processed is placed within an RTP chamber and irradiated by a controlled radiation source, such as a lamp, so that the wafer is heated. Typically, a plurality of lamps is located within the chamber, each lamp irradiating different regions of the semiconductor device. The RTP system also includes at least one temperature sensor, sensing the thermal radiation emitted by regions of the semiconductor device. If the thermal radiation emitted by one region of the semiconductor device is greater than or less than the thermal radiation emitted by other regions, the lamps will decrease or increase the amount of radiation being emitted to that region to achieve a uniform semiconductor device temperature. An example of an RTP system is xe2x80x9cRTP CENTURAxe2x80x9d manufactured by Applied Materials, Inc.
In some cases, the thermal radiation emitted from some wafer regions will be substantially different from other wafer regions, though the lamps heat the regions of the wafer at an equal or substantially equal temperature. Rapid thermal processing is essentially a non-equilibrium thermal process. In particular, edge regions of a wafer contain alignment marks, are masked from process steps such as ion implantation during a stepper job, while a central region of the wafer containing product dies is processed. The processed regions are typically highly doped and are therefore opaque to radiation incident on the wafer surface and exhibit high absorption of radiant energy. Typically, for doping levels below 1xc3x971017 atoms of dopant per cubic centimeter, the semiconductor silicon is transparent or semi-transparent and absorption of irradiated energy is very low. The edge regions of the wafers, which are masked, tend to be transparent or semi-transparent and exhibit low absorption of radiant energy. The greatest radiation intensities are thus normally directed at the semiconductor""s edge regions which dissipate heat more rapidly than the center of the structure. Therefore, the processed and non-processed regions will exhibit substantially different thermal characteristics though heated at the same temperature. The difference in heat emissions between regions of the wafer are sensed by the temperature sensor, which issues a signal to a controller controlling the lamps to reduce or increase power accordingly. As some regions are heated more or less than other neighboring regions, in some cases 30xc2x0 C.-60xc2x0 C. more, thermal stress between regions of the wafer results.
Thermal stress results in warpage, bow or flatness of the semiconductor wafer. Additionally, thermal stress may shift alignment marks that are present on the wafer. Alignment marks are critical in carrying out semiconductor processing steps through photoresist masks during a stepper job. Misalignment between semiconductor device layers created during photoresist masking steps seriously degrades the reliability of the process to perform its intended function.
The following patents describe methods for preventing heating non-uniformities and thermal stress during rapid thermal processing of a semiconductor wafer.
U.S. Pat. No. 5,399,523 to Kakoschke describes a method for rapid thermal processing of a semiconductor by electromagnetic radiation where an irradiation arrangement is provided for heating the semiconductor wafer, which is surrounded by a quartz chamber. The irradiation arrangement has a reflector design that causes the wafer to be irradiated so that a substantially identical temperature is achieved in a middle and edge region.
U.S. Pat. No. 5,851,929 to Thakur et al. describes a method for correcting the shape of a semiconductor structure. Prior to the rapid thermal processing heating step, the shape of the wafer is determined to discern whether and to what extent deformities are present in the wafer""s topography. This information is used to control the heating operation. The radiation emitting zones of a heating assembly are selectively controlled to direct heat radiation of non-uniform intensities toward different regions of the structure to effect non-isothermal conditions within the structure and reduce deformities.
These patents are concerned with altering the RTP system itself or modifying a method of using the RTP system to prevent damage to, or reduce deformities of, a semiconductor substrate.
It is an object of the present invention to provide a method of semiconductor processing that will prevent thermal stress from resulting during rapid thermal processing.
It is a further object of the present invention to provide a method of semiconductor processing that will prevent shifting of alignment marks resulting from rapid thermal processing.
It is another object of the present invention to provide a method for preventing the misalignment of components and interconnection layers in the manufacture of substrates.
The above and other objects have been achieved with a method of processing a semiconductor wafer in a rapid thermal processor where, before rapid thermal processing, a first portion of the wafer, reserved for fabricating an integrated circuit, undergoes doping such that the first portion increases its absorption and decreases its transmission of radiant energy during rapid thermal processing and a second non-fabrication portion of the wafer, having alignment marks, also undergoes doping such that the second portion exhibits increased absorption and decreased transmission of radiant energy during rapid thermal processing. Therefore, no significant variation in thermal emission between portions will occur during rapid thermal processing. Accordingly, uniform heating occurs and thermal stress and shifting of alignment marks is prevented during rapid thermal processing.
This is contrary to methods of the prior art in which the first fabrication portion was doped however, the second non-fabrication portion remained undoped or was only lightly doped. Thus, significant variations in temperature distribution during rapid thermal processing resulted, causing thermal stress and shifting of alignment marks.
It is desirable that heavy doping occurs in both portions such that both first and second portions increase the amount of radiant energy absorbed and decrease the amount of radiant energy transmitted through the portions. Thus, the opacity level of both portions increases as the passage of radiant energy is blocked. Such a dopant level is typically above 1xc3x9710xe2x88x9217 atoms of dopant per cubic centimeter. Dopants, which will increase the level of opacity, are introduced into both portions, for example, during an ion implantation step. The second non-fabrication portion is not masked during a stepper job so that it may receive the dopants. In one example, the second non-fabrication portion receives the same implant at the same dose and energy as the first fabrication portion. In another example, atoms at a dose and an energy level sufficient to cause surface level amorphization in the first fabrication portion and the second non-fabrication portion are used for doping. An equal extent of amorphous or polycrystalline layer formation may occur in each portion.
After doping occurs in both portions, the semiconductor wafer is inserted into a rapid thermal processor. The rapid thermal processor includes at least one sensor, and, in one example, a plurality of sensors, sensing the radiation emitted by the wafer. Because both the first and second portions have undergone doping, more radiant energy is absorbed and less radiant energy is transmitted at both portions. The sensor thus detects no significant variation in heat emission between the first and second portions. Therefore, the sensor will signal the radiation source to heat the portions at the same temperature, or at temperatures where no significant temperature variation between the first fabrication portion and the second non-fabrication portion results. A significant temperature variation is considered to be a temperature at which thermal stress between portions will occur. Therefore, the radiation source heats the first and second doped portions such that no significant temperature variation between portions occurs. Thus, thermal stress between the doped portions and shifting of alignment marks is prevented.
In later processing steps, semiconductor device layers are accurately aligned as alignment marks, such as global alignment marks, used for aligning the wafer to a stepper, remain in the same location or within a location that is within the correction limits of the stepper.
In one embodiment of the invention, before rapid thermal processing, the first fabrication portion undergoes doping to form source, drain and gate regions and, in accordance with the present invention, the second non-fabrication portion also undergo doping such that both portions increase their absorption levels during rapid thermal processing. Therefore, thermal stress and shifting of alignment marks within the first portion is prevented.